1. Technical Field
The description relates to a liquid crystal display and driving method thereof, and more particularly, to a liquid crystal display capable of stabilizing high voltage drop provided across opposite sides of a liquid crystal layer and driving method thereof.
2. Description of the Related Art
Liquid crystal displays (LCDs) have advantages of a thin profile, low power consumption, and low radiation, and are broadly adopted for application in media players, mobile phones, personal digital assistants (PDAs), computer displays, and flat screen televisions. The operation of a liquid crystal display is featured by modulating the voltage drop across opposite sides of a liquid crystal layer for twisting the angles of liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of light source provided by a backlight module. With the aim of enhancing display quality of liquid crystal displays, utilization of blue phase (BP) liquid crystal to achieve super-high frame rate and super-wide viewing angle has gained more and more attractiveness. However, in the operation of BP-mode liquid crystal displays, the voltage drop required for twisting the angles of BP liquid crystal molecules is significantly greater than the voltage drop required for twisting the angles of conventional liquid crystal molecules. For that reason, the driving circuit of conventional liquid crystal displays cannot meet the driving requirement of BP-mode liquid crystal displays.
FIG. 1 is a circuit embodiment diagram schematically showing a BP-mode liquid crystal display using prior-art driving circuit. As shown in FIG. 1, the BP-mode liquid crystal display 100 includes a plurality of data lines 102, a plurality of gate lines 104, and a plurality of pixel units 110. In the operation of pixel unit PUn_m, the first data switch SW1 is utilized for outputting a first electrode voltage Vp1 according to a gate signal SGn and a data signal SDm, the first storage capacitor Cst1 is employed to store the first electrode voltage Vp1, the second data switch SW2 is utilized for outputting a second electrode voltage Vp2 according to the gate signal SGn and a data signal SDm+1, and the second storage capacitor Cst2 is employed to store the second electrode voltage Vp2. Further, the first common voltage Vcom1 can be employed to adjust the first electrode voltage Vp1 through coupling of the first storage capacitor Cst1, and the second common voltage Vcom2 can be employed to adjust the second electrode voltage Vp2 through coupling of the second storage capacitor Cst2, for enlarging voltage difference between the first electrode voltage Vp1 and the second electrode voltage Vp2, such that the voltage drop across opposite sides of the liquid crystal capacitor Clc can be employed to control the transmittance of a BP liquid crystal layer.
FIG. 2 is a schematic diagram showing related signal waveforms regarding the operation of the BP-mode liquid crystal display 100 illustrated in FIG. 1, having time along the abscissa. The signal waveforms in FIG. 2, from top to bottom, are the gate signal SGn, the first common voltage Vcom1, the first electrode voltage Vp1, the second common voltage Vcom2, and the second electrode voltage Vp2. Referring to FIG. 2 in conjunction with FIG. 1, during an interval T1, the first electrode voltage Vp1 is set to a first high voltage VH1 by the first data switch SW1 according to the data signal SDm and the gate pulse of the gate signal SGn, and the second electrode voltage Vp2 is set to a first low voltage VL1 by the second data switch SW2 according to the data signal SDm+1 and the gate pulse of the gate signal SGn. During an interval T2, the first electrode voltage Vp1 is pulled down to a second high voltage VH2 by the falling edge of the gate pulse through coupling of the device capacitor of the first data switch SW1, and the second electrode voltage Vp2 is pulled down to a second low voltage VL2 by the falling edge of the gate pulse through coupling of the device capacitor of the second data switch SW2. During an interval T3, the first electrode voltage Vp1 is pulled up to a third high voltage VH3 by the rising edge of the first common voltage Vcom1 through coupling of the first storage capacitor Cst1, and the second electrode voltage Vp2 is pulled down to a third low voltage VL3 by the falling edge of the second common voltage Vcom2 through coupling of the second storage capacitor Cst2, for enlarging voltage difference between the first electrode voltage Vp1 and the second electrode voltage Vp2. However, after the interval T3, the rising/falling edge of the first common voltage Vcom1 still has an effect on the first electrode voltage Vp1, and the rising/falling edge of the second common voltage Vcom2 still has an effect on the second electrode voltage Vp2, which is likely to cause the phenomena of flickering and color-shift on LCD screen.